Analog IC Layout Design Engineer

Job Description

1. Work and lead junior engineer towards projects delivery with other layout and circuit design engineers to
   resolve any technical issues that will affect layout to ensure high quality.
2. Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout
   activities as cell and block level creation, edit and full verification.
3. Use state-of-the-art layout techniques for matching, ESD, latch-up prevention and parasitic reduction and work
   with an awareness and understanding of the process from physical point of view.
4. Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
5. Where possible, use schematic driven layout and consider top level auto routing.
6. Involve in review session and prepare all related document and data preparation for wafer tape out

1. Layout & EDA tool skill: at least 1 year of design experience as product sub leader
2. Layout & EDA tool skill: Expertise with Cadence and Synopsys
3. Willing to put extra effort to keep the project schedule.
4. At least have a minimum of 3-5 years’ experience in Analog IC layout design.
5. Willing to work flexible hours to support different time zone teams.
6. Willing to relocate to Malaysia or other country to support Design Team.
7. Need to work onsite.
8. Must have good verbal and written communication skills in English.
9. Good interpersonal, communication, and collaboration skills